1. Field of the Invention
The present invention relates to a Phase Locked Loop (PLL) frequency synthesizer for multi-band applications and, more specifically, to a circuit that uses only one voltage-controlled oscillator (VCO), but generates two or more output frequency ranges.
2. Description of Related Art
FIG. 1 illustrates a standard Phase-Locked Loop (PLL) block diagram. The basic PLL has an input frequency f.sub.in 2 which is divided by a divider 4, wherein the divider 4 divides the input frequency f.sub.in 2 by a value N. The output of the divider 4 is then input into a phase detector 6. The phase detector 6 outputs a voltage that is proportional to a phase difference between two input frequencies. This phase detector output voltage is then input into a loop filter 8. The loop filter 8 smoothes the phase detector output voltage and determines the loop performance based upon selected loop filter values. The output of the loop filter 8 adjusts the voltage-controlled oscillator (VCO) 10 and determines the output frequency of the VCO 10. The output of the of the VCO 10 is then fed back as an input to the phase detector 6 via a feedback loop 14. The output voltage of the phase detector 6 will vary according to any change in the phase difference between the output frequency of the VCO 10 and the input frequency f.sub.in 2.
The feedback loop 14 thus provides a means of "locking" the phase of the output frequency f.sub.out 12 in accordance with the phase of the input frequency f.sub.in 2. If the input frequency f.sub.in 2 is a highly stable reference frequency, the PLL circuit produces a highly stable output frequency f.sub.in 12. The PLL circuit produces an output frequency f.sub.out 12, equal to the value [f.sub.in / N], wherein the phase of the VCO output frequency f.sub.out 12 follows the phase of the input frequency f.sub.in 2.
As illustrated in FIG. 2, a divider 16 may be used in the feedback loop 14 in order to change the output frequency f.sub.out 12. In this case, the output frequency f.sub.out 12 from the VCO 10 is equal to the value [(f.sub.in * M)/N]. If the divider 16 is implemented using a programmable counter, the value of M can be changed. Thus, the output frequency f.sub.out 12 can be adjusted to a desired value by varying the value of "M."
Referring now to FIG. 3, an application of a PLL circuit is shown. A phase modulated intermediate input frequency (IF) 18 is input to the first divider 4 of the PLL circuit. The feedback loop 14 contains two additional blocks, however. A mixer 22 mixes a local oscillator signal RF.sub.LO 26 with the RF.sub.OUT signal 20 and the output of the mixer 22 is input into a bandpass (BP) filter 24. The output of the mixer may be referred to as the "feedback frequency." The feedback frequency can be selected from one of the numerous frequencies produced by the harmonic mixing. In general, the output of the mixer is equal to [.+-.n*RF.sub.OUT .+-.m*RF.sub.LO ]. If n and m are "1," then the selected outputs of the mixer are either RF.sub.out --RF.sub.LO or RF.sub.LO --RF.sub.OUT (assuming frequency down-conversion). The bandpass filter 24 removes any unwanted mixing products produced by the mixer 22 and determines which frequency is fed-back through the M divider 16. The operation of the remaining blocks operate as described in the previous figures. The PLL circuit translates i.e., moves) the frequency of the input IF 18 frequency to the VCO frequency with the same phase. Thus, by adjusting the value of the R.sub.FLO frequency 26, a desired output frequency RF.sub.out 20 can be produced for a given intermediate frequency (IF) 18.
In the following general equations, f.sub.fb is the feedback frequency output by the mixer, f.sub.VCO is the VCO frequency, and f.sub.in is the input frequency. The variables "n" and "m" are integer multipliers introuced by the harmonic mixing. These equations illustrate the operation of the circuit shown in FIG. 3. ##EQU1##
For applications that require two different RF.sub.out frequency bands, such as a dual-band cellular telephone, a second PLL circuit would normally be required. For example, in a GSM/DCS 1800 dual-band cellular telephone, the transmit frequency bands are 890 -915 MHz for the GSM band and 1710 -1785 MHz for the DCS 1800 band. This would require using two separate VCOs, which adds complexity and expense to the over-all system design. Thus, it would be desirable to have a PLL circuit which could generate two different output frequency bands, while using only one VCO.